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1. general description the lpc2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit arm7tdmi-s cpu with real-time emulation that combines the microcontroller with up to 512 kb of embedded high-speed flash memory. a 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. for critical performance in inte rrupt service routines and dsp algorithms, this increases performance up to 30 % over thumb mode. for critical code size applications, the alternative 16-bit thumb mode reduces code by more than 30 % with minimal performance penalty. the lpc2364/65/66/67/68 are ideal for multi- purpose serial communication applications. they incorporate a 10/100 ethernet media access controller (mac), usb full speed device with 4 kb of endpoint ram (lpc2364/6 6/68 only), four uarts, two can channels (lpc2364/66/68 only), an sp i interface, two synchronou s serial ports (ssp), three i 2 c-bus interfaces, and an i 2 s-bus interface. this ble nd of serial communications interfaces combined with an on-chip 4 mhz internal oscilla tor, sram of up to 32 kb, 16 kb sram for ethernet, 8 kb sram for usb and general purpose use, together with 2 kb battery powered sram make these devices very well suited for communication gateways and protocol converters. various 32-bit timers , an improved 10-bit adc, 10-bit dac, one pwm unit, a can control unit (lpc2364/66/68 only ), and up to 70 fast gpio lines with up to 12 edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2. features and benefits ? arm7tdmi-s processor, running at up to 72 mhz ? up to 512 kb on-chip flash program memory with in-system programming (isp) and in-application programming (i ap) capabilities. flash program memory is on the arm local bus for high performance cpu access. ? 8 kb/32 kb of sram on the arm local bus for high performance cpu access. ? 16 kb sram for ethernet interface. can also be used as general purpose sram. ? 8 kb sram for general purpose dma use also accessible by the usb. ? dual advanced high-performance bus (ahb) system that provides for simultaneous ethernet dma, usb dma, and program ex ecution from on-chip flash with no contention between those functions. a bus bridge allows the ethernet dma to access the other ahb subsystem. ? advanced vectored interrupt controller (vic), supporting up to 32 vectored interrupts. ? general purpose dma contro ller (gpdma) on ahb that can be used with the ssp serial interfaces, the i 2 s port, and the secure digital/multimediacard (sd/mmc) card port, as well as for memory-to-memory transfers. lpc2364/65/66/67/68 single-chip 16-bit/32-bit microco ntrollers; up to 512 kb flash with isp/iap, ethernet, usb 2.0, can, and 10-bit adc/dac rev. 7.1 ? 16 october 2013 product data sheet
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 2 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers ? serial interfaces: ? ethernet mac with associated dma controller. these functions reside on an independent ahb. ? usb 2.0 full-speed device with on-chip phy and associated dma controller (lpc2364/66/68 only). ? four uarts with fractional baud rate generation, one with modem control i/o, one with irda support, all with fifo. ? can controller with two channels (lpc2364/66/68 only). ? spi controller. ? two ssp controllers, with fifo and multi-protocol capabilities. one is an alternate for the spi port, sharing its interrupt and pins. these can be used with the gpdma controller. ? three i 2 c-bus interfaces (one with open-drai n and two with standard port pins). ? i 2 s (inter-ic sound) interface for digital audio input or output. it can be used with the gpdma. ? other peripherals: ? sd/mmc memory card inte rface (lpc2367/68 only). ? 70 general purpose i/o pins with configurable pull-up/down resistors. ? 10-bit adc with input multiplexing among 6 pins. ? 10-bit dac. ? four general purpose timers/counters with a total of 8 capture inputs and 10 compare outputs. each timer block has an external count input. ? one pwm/timer block with support for th ree-phase motor control. the pwm has two external count inputs. ? real-time clock (rtc) with separate power pin, clo ck source can be the rtc oscillator or the apb clock. ? 2 kb sram powered from the rtc power pin, allowing data to be stored when the rest of the chip is powered off. ? watchdog timer (wdt). the wdt can be cl ocked from the internal rc oscillator, the rtc oscillator, or the apb clock. ? standard arm test/debug interface for compatibility with existing tools. ? emulation trace module supports real-time trace. ? single 3.3 v power supply (3.0 v to 3.6 v). ? four reduced power modes: idle, sleep, power-down, and deep power-down. ? four external interrupt inputs configurable as edge/level sensitive. all pins on port 0 and port 2 can be used as edge sensitive interrupt sources. ? processor wake-up from power-down mode via any interrupt able to operate during power-down mode (includes external interrupts, rtc interrupt, usb activity, ethernet wake-up interrupt). ? two independent power domains allow fine tuning of power consumption based on needed features. ? each peripheral has it s own clock divider for further power saving. ? brownout detect with separate thresholds for interrupt and forced reset. ? on-chip power-on reset. ? on-chip crystal oscillator with an op erating range of 1 mhz to 24 mhz. ? 4 mhz internal rc oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. when used as the cpu clock, does not allow can and usb to run.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 3 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers ? on-chip pll allows cpu operation up to the maximum cpu rate without the need for a high frequency crystal. may be run from the main oscillator, the internal rc oscillator, or the rtc oscillator. ? boundary scan for simplified board testing is available in lpc2364fet100 and lpc2368fet100 (tfbga package). ? versatile pin function selections allow mo re possibilities for using on-chip peripheral functions. 3. applications ? industrial control ? medical systems ? protocol converter ? communications 4. ordering information table 1. ordering information type number package name description version lpc2364fbd100 lqfp100 plastic low profile q uad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc2364hbd100 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc2364fet100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc2365fbd100 lqfp100 plastic low profile q uad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc2366fbd100 lqfp100 plastic low profile q uad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc2367fbd100 lqfp100 plastic low profile q uad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc2368fbd100 lqfp100 plastic low profile q uad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc2368fet100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 4 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 4.1 ordering options table 2. ordering options type number flash (kb) sram (kb) ethernet usb device + 4kb fifo sd/mmc gp dma channels temp range local bus ethernet buffers gp/usb rtc total can adc dac lpc2364fbd100 128 8 16 8 2 34 rmii yes no yes 2 6 1 ? 40 ? c to +85 ?c lpc2364hbd100 128 8 16 8 2 34 rmii yes no yes 2 6 1 ? 40 ? c to +125 ?c lpc2364fet100 128 8 16 8 2 34 rmii yes no yes 2 6 1 ? 40 ? c to +85 ?c lpc2365fbd100 256 32 16 8 2 58 rmii no no yes - 6 1 ? 40 ? c to +85 ?c lpc2366fbd100 256 32 16 8 2 58 rmii yes no yes 2 6 1 ? 40 ? c to +85 ?c lpc2367fbd100 512 32 16 8 2 58 rmii no yes yes - 6 1 ? 40 ? c to +85 ?c lpc2368fbd100 512 32 16 8 2 58 rmii yes yes yes 2 6 1 ? 40 ? c to +85 ?c lpc2368fet100 512 32 16 8 2 58 rmii yes yes yes 2 6 1 ? 40 ? c to +85 ?c
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 5 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 5. block diagram (1) lpc2367/68 only. (2) lpc2364/66/68 only. fig 1. lpc2364/65/66/67/68 block diagram pwm1 arm7tdmi-s pll eint3 to eint0 flash p3, p4 p0, p1, p2, legacy gpi/o 52 pins total p0, p1 sck, sck0 mosi, mosi0 ssel, ssel0 sck1 mosi1 miso1 ssel1 scl0, scl1, scl2 i2srx_clk i2stx_clk i2srx_ws i2stx_ws 6 ad0 rtcx1 rtcx2 mciclk, mcipwr rxd0, rxd2, rxd3 txd1 rxd1 rd1, rd2 td1, td2 can1, can2 (2) usb_d+, usb_d? xtal1 tck tdo extin0 xtal2 reset trst tditms high-speed gpi/o 70 pins total lpc2364/65/66/67/68 8/32 kb sram 128/256/ 512 kb flash internal controllers test/debug interface emulation trace module trace signals ahb bridge ahb bridge ethernet mac with dma 16 kb sram master port ahb to ahb bridge slave port system clock system functions internal rc oscillator v dda v dd(3v3) vref v ssa , v ss vectored interrupt controller 8 kb sram usb with 4 kb ram and dma (2) gp dma controller i 2 s interface spi, ssp0 interface i2srx_sda i2stx_sda miso, miso0 ssp1 interface sd/mmc card interface (1) mcicmd, mcidat[3:0] txd0, txd2, txd3 uart0, uart2, uart3 uart1 dtr1, rts1 dsr1, cts1, dcd1, ri1 i 2 c0, i 2 c1, i 2 c2 sda0, sda1, sda2 external interrupts capture/compare timer0/timer1/ timer2/timer3 a/d converter d/a converter 2 kb battery ram rtc oscillator real- time clock watchdog timer system control 2 cap0/cap1/ cap2/cap3 4 mat2, 2 mat0/mat1/ mat3 6 pwm1 2 pcap1 aout vbat ahb to apb bridge sram rmii(8) v bus usb_connect usb_up_led 002aac566 p0, p2 power domain 2 ahb2 ahb1 power domain 2 v dd(dcdc)(3v3)
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 6 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 6. pinning information 6.1 pinning fig 2. lpc2364/65/66/67/68 pinning fig 3. lpc2364/68 pinning TFBGA100 package lpc2364fbd100 lpc2365fbd100 lpc2366fbd100 lpc2367fbd100 lpc2368fbd100 75 26 50 100 76 51 1 25 002aac576 002aad225 lpc2364fet100/lpc2368fet100 transparent top view j g k h f e d c b a 246810 13579 ball a1 index area
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 7 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers table 3. pin allocation table pin symbol pin symbol pin symbol pin symbol row a 1tdo 2p0[3]/rxd0 3v dd(3v3) 4 p1[4]/enet_tx_en 5 p1[10]/enet_rxd1 6 p1[16]/enet_mdc 7 v dd(dcdc)(3v3) 8 p0[4]/i2srx_clk/ rd2/cap2[0] 9 p0[7]/i2stx_clk/ sck1/mat2[1] 10 p0[9]/i2stx_sda/ mosi1/mat2[3] 11 - 12 - row b 1tms 2rtck 3v ss 4 p1[1]/enet_txd1 5 p1[9]/enet_rxd0 6 p1[17]/ enet_mdio 7v ss 8 p0[6]/i2srx_sda/ ssel1/mat2[0] 9 p2[0]/pwm1[1]/ txd1/traceclk 10 p2[1]/pwm1[2]/ rxd1/pipestat0 11 - 12 - row c 1tck 2trst 3 tdi 4 p0[2]/txd0 5 p1[8]/enet_crs 6 p1[15]/ enet_ref_clk 7 p4[28]/mat2[0]/ txd3 8 p0[8]/i2stx_ws/ miso1/mat2[2] 9v ss 10 v dd(3v3) 11 - 12 - row d 1 p0[24]/ad0[1]/ i2srx_ws/cap3[1] 2 p0[25]/ad0[2]/ i2srx_sda/txd3 3 p0[26]/ad0[3]/ aout/rxd3 4 dbgen 5 p1[0]/enet_txd0 6 p1[14]/en et_rx_er 7 p0[5]/i2srx_ws/ td2/cap2[1] 8 p2[2]/pwm1[3]/ cts1/pipestat1 9 p2[4]/pwm1[5]/ dsr1/tracesync 10 p2[5]/pwm1[6]/ dtr1/tracepkt0 11 - 12 - row e 1v ssa 2v dda 3vref 4v dd(dcdc)(3v3) 5 p0[23]/ad0[0]/ i2srx_clk/cap3[0] 6 p4[29]/mat2[1]/ rxd3 7 p2[3]/pwm1[4]/ dcd1/pipestat2 8 p2[6]/pcap1[0]/ri1/ tracepkt1 9 p2[7]/rd2/ rts1/tracepkt2 10 p2[8]/td2/ txd2/tracepkt3 11 - 12 - row f 1v ss 2 rtcx1 3 reset 4 p1[31]/sck1/ ad0[5] 5 p1[21]/pwm1[3]/ ssel0 6 p0[18]/dcd1/ mosi0/mosi 7 p2[9]/usb_connect/ rxd2/extin0 8 p0[16]/rxd1/ ssel0/ssel 9 p0[17]/cts1/ miso0/miso 10 p0[15]/txd1/ sck0/sck 11 - 12 - row g 1 rtcx2 2 vbat 3 xtal2 4 p0[30]/usb_d ? 5 p1[25]/mat1[1] 6 p1[29]/pcap1[1]/ mat0[1] 7v ss 8 p0[21]/ri1/ mcipwr/rd1 9 p0[20]/dtr1/ mcicmd/scl1 10 p0[19]/dsr1/ mciclk/sda1 11 - 12 - row h
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 8 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 1 p1[30]/v bus / ad0[4] 2 xtal1 3 p3[25]/mat0[0]/ pwm1[2] 4 p1[18]/usb_up_led/ pwm1[1]/cap1[0] 5 p1[24]/pwm1[5]/ mosi0 6v dd(dcdc)(3v3) 7 p0[10]/txd2/ sda2/mat3[0] 8p2[11]/eint1 / mcidat1/i2stx_clk 9v dd(3v3) 10 p0[22]/rts1/ mcidat0/td1 11 - 12 - table 3. pin allocation table ?continued pin symbol pin symbol pin symbol pin symbol
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 9 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers row j 1 p0[28]/scl0 2 p0[27]/sda0 3 p0 [29]/usb_d+ 4 p1[19]/cap1[1] 5 p1[22]/mat1[0] 6 v ss 7 p1[28]/pcap1[0]/ mat0[0] 8 p0[1]/td1/rxd3/scl1 9 p2[13]/eint3 / mcidat3/i2stx_sda 10 p2[10]/eint0 11 - 12 - row k 1 p3[26]/mat0[1]/ pwm1[3] 2v dd(3v3) 3v ss 4 p1[20]/pwm1[2]/ sck0 5 p1[23]/pwm1[4]/ miso0 6 p1[26]/pwm1[6]/ cap0[0] 7 p1[27]/cap0[1] 8 p0 [0]/rd1/txd3/sda1 9 p0[11]/rxd2/ scl2/mat3[1] 10 p2[12]/eint2 / mcidat2/i2stx_ws 11 - 12 - table 3. pin allocation table ?continued pin symbol pin symbol pin symbol pin symbol
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 10 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 6.2 pin description table 4. pin description symbol pin ball type description p0[0] to p0[31] i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 0 pins depends upon the pin function selected via the pin connect block. pins 12, 13, 14, and 31 of this port are not available. p0[0]/rd1/txd3/ sda1 46 [1] k8 [1] i/o p0[0] ? general purpose digital input/output pin. i rd1 ? can1 receiver input. (lpc2364/66/68 only) o txd3 ? transmitter output for uart3. i/o sda1 ? i 2 c1 data input/output (this is not an open-drain pin). p0[1]/td1/rxd3/ scl1 47 [1] j8 [1] i/o p0[1] ? general purpose digital input/output pin. o td1 ? can1 transmitter output. (lpc2364/66/68 only) i rxd3 ? receiver input for uart3. i/o scl1 ? i 2 c1 clock input/output (this is not an open-drain pin). p0[2]/txd0 98 [1] c4 [1] i/o p0[2] ? general purpose digital input/output pin. o txd0 ? transmitter output for uart0. p0[3]/rxd0 99 [1] a2 [1] i/o p0[3] ? general purpose digital input/output pin. i rxd0 ? receiver input for uart0. p0[4]/ i2srx_clk/ rd2/cap2[0] 81 [1] a8 [1] i/o p0[4] ? general purpose digital input/output pin. i/o i2srx_clk ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i rd2 ? can2 receiver input. (lpc2364/66/68 only) i cap2[0] ? capture input for timer 2, channel 0. p0[5]/ i2srx_ws/ td2/cap2[1] 80 [1] d7 [1] i/o p0[5] ? general purpose digital input/output pin. i/o i2srx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o td2 ? can2 transmitter output. (lpc2364/66/68 only) i cap2[1] ? capture input for timer 2, channel 1. p0[6]/ i2srx_sda/ ssel1/mat2[0] 79 [1] b8 [1] i/o p0[6] ? general purpose digital input/output pin. i/o i2srx_sda ? receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o ssel1 ? slave select for ssp1. o mat2[0] ? match output for timer 2, channel 0. p0[7]/ i2stx_clk/ sck1/mat2[1] 78 [1] a9 [1] i/o p0[7] ? general purpose digital input/output pin. i/o i2stx_clk ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i/o sck1 ? serial clock for ssp1. o mat2[1] ? match output for timer 2, channel 1. p0[8]/ i2stx_ws/ miso1/mat2[2] 77 [1] c8 [1] i/o p0[8] ? general purpose digital input/output pin. i/o i2stx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o miso1 ? master in slave out for ssp1. o mat2[2] ? match output for timer 2, channel 2.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 11 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers p0[9]/ i2stx_sda/ mosi1/mat2[3] 76 [1] a10 [1] i/o p0[9] ? general purpose digital input/output pin. i/o i2stx_sda ? transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o mosi1 ? master out slave in for ssp1. o mat2[3] ? match output for timer 2, channel 3. p0[10]/txd2/ sda2/mat3[0] 48 [1] h7 [1] i/o p0[10] ? general purpose digital input/output pin. o txd2 ? transmitter output for uart2. i/o sda2 ? i 2 c2 data input/output (this is not an open-drain pin). o mat3[0] ? match output for timer 3, channel 0. p0[11]/rxd2/ scl2/mat3[1] 49 [1] k9 [1] i/o p0[11] ? general purpose digital input/output pin. i rxd2 ? receiver input for uart2. i/o scl2 ? i 2 c2 clock input/output (this is not an open-drain pin). o mat3[1] ? match output for timer 3, channel 1. p0[15]/txd1/ sck0/sck 62 [1] f10 [1] i/o p0[15] ? general purpose digital input/output pin. o txd1 ? transmitter output for uart1. i/o sck0 ? serial clock for ssp0. i/o sck ? serial clock for spi. p0[16]/rxd1/ ssel0/ssel 63 [1] f8 [1] i/o p0[16] ? general purpose digital input/output pin. i rxd1 ? receiver input for uart1. i/o ssel0 ? slave select for ssp0. i/o ssel ? slave select for spi. p0[17]/cts1/ miso0/miso 61 [1] f9 [1] i/o p0[17] ? general purpose digital input/output pin. i cts1 ? clear to send input for uart1. i/o miso0 ? master in slave out for ssp0. i/o miso ? master in slave out for spi. p0[18]/dcd1/ mosi0/mosi 60 [1] f6 [1] i/o p0[18] ? general purpose digital input/output pin. i dcd1 ? data carrier detect input for uart1. i/o mosi0 ? master out slave in for ssp0. i/o mosi ? master out slave in for spi. p0[19]/dsr1/ mciclk/sda1 59 [1] g10 [1] i/o p0[19] ? general purpose digital input/output pin. i dsr1 ? data set ready input for uart1. o mciclk ? clock output line for sd/mmc interface. (lpc2367/68 only) i/o sda1 ? i 2 c1 data input/output (this is not an open-drain pin). p0[20]/dtr1/ mcicmd/scl1 58 [1] g9 [1] i/o p0[20] ? general purpose digital input/output pin. o dtr1 ? data terminal ready output for uart1. i mcicmd ? command line for sd/mmc interface. (lpc2367/68 only) i/o scl1 ? i 2 c1 clock input/output (this is not an open-drain pin). table 4. pin description ?continued symbol pin ball type description
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 12 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers p0[21]/ri1/ mcipwr/rd1 57 [1] g8 [1] i/o p0[21] ? general purpose digital input/output pin. i ri1 ? ring indicator i nput for uart1. o mcipwr ? power supply enable for external sd/mmc power supply. (lpc2367/68 only) i rd1 ? can1 receiver input. (lpc2364/66/68 only) p0[22]/rts1/ mcidat0/td1 56 [1] h10 [1] i/o p0[22] ? general purpose digital input/output pin. o rts1 ? request to send output for uart1. o mcidat0 ? data line for sd/mmc interface. (lpc2367/68 only) o td1 ? can1 transmitter output. (lpc2364/66/68 only) p0[23]/ad0[0]/ i2srx_clk/ cap3[0] 9 [2] e5 [2] i/o p0[23] ? general purpose digital input/output pin. i ad0[0] ? a/d converter 0, input 0. i/o i2srx_clk ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i cap3[0] ? capture input for timer 3, channel 0. p0[24]/ad0[1]/ i2srx_ws/ cap3[1] 8 [2] d1 [2] i/o p0[24] ? general purpose digital input/output pin. i ad0[1] ? a/d converter 0, input 1. i/o i2srx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i cap3[1] ? capture input for timer 3, channel 1. p0[25]/ad0[2]/ i2srx_sda/ txd3 7 [2] d2 [2] i/o p0[25] ? general purpose digital input/output pin. i ad0[2] ? a/d converter 0, input 2. i/o i2srx_sda ? receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o txd3 ? transmitter output for uart3. p0[26]/ad0[3]/ aout/rxd3 6 [3] d3 [3] i/o p0[26] ? general purpose digital input/output pin. i ad0[3] ? a/d converter 0, input 3. o aout ? d/a converter output. i rxd3 ? receiver input for uart3. p0[27]/sda0 25 [4] j2 [4] i/o p0[27] ? general purpose digital input/output pin. output is open-drain. i/o sda0 ? i 2 c0 data input/output. open-drain output (for i 2 c-bus compliance). p0[28]/scl0 24 [4] j1 [4] i/o p0[28] ? general purpose digital input/output pin. output is open-drain. i/o scl0 ? i 2 c0 clock input/output. open-drain output (for i 2 c-bus compliance). p0[29]/usb_d+ 29 [5] j3 [5] i/o p0[29] ? general purpose digital input/output pin. i/o usb_d+ ? usb bidirectional d+ line. (lpc2364/66/68 only) p0[30]/usb_d ? 30 [5] g4 [5] i/o p0[30] ? general purpose digital input/output pin. i/o usb_d ? ? usb bidirectional d ? line. (lpc2364/66/68 only) p1[0] to p1[31] i/o port 1: port 1 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. table 4. pin description ?continued symbol pin ball type description
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 13 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers p1[0]/ enet_txd0 95 [1] d5 [1] i/o p1[0] ? general purpose digital input/output pin. o enet_txd0 ? ethernet transmit data 0. p1[1]/ enet_txd1 94 [1] b4 [1] i/o p1[1] ? general purpose digital input/output pin. o enet_txd1 ? ethernet transmit data 1. p1[4]/ enet_tx_en 93 [1] a4 [1] i/o p1[4] ? general purpose digital input/output pin. o enet_tx_en ? ethernet transmit data enable. p1[8]/ enet_crs 92 [1] c5 [1] i/o p1[8] ? general purpose digital input/output pin. i enet_crs ? ethernet carrier sense. p1[9]/ enet_rxd0 91 [1] b5 [1] i/o p1[9] ? general purpose digital input/output pin. i enet_rxd0 ? ethernet receive data. p1[10]/ enet_rxd1 90 [1] a5 [1] i/o p1[10] ? general purpose digital input/output pin. i enet_rxd1 ? ethernet receive data. p1[14]/ enet_rx_er 89 [1] d6 [1] i/o p1[14] ? general purpose digital input/output pin. i enet_rx_er ? ethernet receive error. p1[15]/ enet_ref_clk 88 [1] c6 [1] i/o p1[15] ? general purpose digital input/output pin. i enet_ref_clk ? ethernet reference clock. p1[16]/ enet_mdc 87 [1] a6 [1] i/o p1[16] ? general purpose digital input/output pin. o enet_mdc ? ethernet miim clock. p1[17]/ enet_mdio 86 [1] b6 [1] i/o p1[17] ? general purpose digital input/output pin. i/o enet_mdio ? ethernet miim data input and output. p1[18]/ usb_up_led/ pwm1[1]/ cap1[0] 32 [1] h4 [1] i/o p1[18] ? general purpose digital input/output pin. o usb_up_led ? usb goodlink led indicator. it is low when device is configured (non-control endpoints enabled), or when host is enabled and has detected a device on the bus. it is high when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. it transitions between low and high (flashes) when host is enabled and detects activity on the bus. (lpc2364/66/68 only) o pwm1[1] ? pulse width modulator 1, channel 1 output. i cap1[0] ? capture input for timer 1, channel 0. p1[19]/cap1[1] 33 [1] j4 [1] i/o p1[19] ? general purpose digital input/output pin. i cap1[1] ? capture input for timer 1, channel 1. p1[20]/pwm1[2]/ sck0 34 [1] k4 [1] i/o p1[20] ? general purpose digital input/output pin. o pwm1[2] ? pulse width modulator 1, channel 2 output. i/o sck0 ? serial clock for ssp0. p1[21]/pwm1[3]/ ssel0 35 [1] f5 [1] i/o p1[21] ? general purpose digital input/output pin. o pwm1[3] ? pulse width modulator 1, channel 3 output. i/o ssel0 ? slave select for ssp0. p1[22]/mat1[0] 36 [1] j5 [1] i/o p1[22] ? general purpose digital input/output pin. o mat1[0] ? match output for timer 1, channel 0. table 4. pin description ?continued symbol pin ball type description
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 14 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers p1[23]/pwm1[4]/ miso0 37 [1] k5 [1] i/o p1[23] ? general purpose digital input/output pin. o pwm1[4] ? pulse width modulator 1, channel 4 output. i/o miso0 ? master in slave out for ssp0. p1[24]/pwm1[5]/ mosi0 38 [1] h5 [1] i/o p1[24] ? general purpose digital input/output pin. o pwm1[5] ? pulse width modulator 1, channel 5 output. i/o mosi0 ? master out slave in for ssp0. p1[25]/mat1[1] 39 [1] g5 [1] i/o p1[25] ? general purpose digital input/output pin. o mat1[1] ? match output for timer 1, channel 1. p1[26]/pwm1[6]/ cap0[0] 40 [1] k6 [1] i/o p1[26] ? general purpose digital input/output pin. o pwm1[6] ? pulse width modulator 1, channel 6 output. i cap0[0] ? capture input for timer 0, channel 0. p1[27]/cap0[1] 43 [1] k7 [1] i/o p1[27] ? general purpose digital input/output pin. i cap0[1] ? capture input for timer 0, channel 1. p1[28]/ pcap1[0]/ mat0[0] 44 [1] j7 [1] i/o p1[28] ? general purpose digital input/output pin. i pcap1[0] ? capture input for pwm1, channel 0. o mat0[0] ? match output for timer 0, channel 0. p1[29]/ pcap1[1]/ mat0[1] 45 [1] g6 [1] i/o p1[29] ? general purpose digital input/output pin. i pcap1[1] ? capture input for pwm1, channel 1. o mat0[1] ? match output for timer 0, channel 0. p1[30]/v bus / ad0[4] 21 [2] h1 [2] i/o p1[30] ? general purpose digital input/output pin. i v bus ? monitors the presence of usb bus power. (lpc2364/66/68 only) note: this signal must be high for usb reset to occur. i ad0[4] ? a/d converter 0, input 4. p1[31]/sck1/ ad0[5] 20 [2] f4 [2] i/o p1[31] ? general purpose digital input/output pin. i/o sck1 ? serial clock for ssp1. i ad0[5] ? a/d converter 0, input 5. p2[0] to p2[31] i/o port 2: port 2 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 2 pins depends upon the pin function selected via the pin connect block. pins 14 through 31 of this port are not available. p2[0]/pwm1[1]/ txd1/ traceclk 75 [1] b9 [1] i/o p2[0] ? general purpose digital input/output pin. o pwm1[1] ? pulse width modulator 1, channel 1 output. o txd1 ? transmitter output for uart1. o traceclk ? trace clock. p2[1]/pwm1[2]/ rxd1/ pipestat0 74 [1] b10 [1] i/o p2[1] ? general purpose digital input/output pin. o pwm1[2] ? pulse width modulator 1, channel 2 output. i rxd1 ? receiver input for uart1. o pipestat0 ? pipeline status, bit 0. p2[2]/pwm1[3]/ cts1/ pipestat1 73 [1] d8 [1] i/o p2[2] ? general purpose digital input/output pin. o pwm1[3] ? pulse width modulator 1, channel 3 output. i cts1 ? clear to send input for uart1. o pipestat1 ? pipeline status, bit 1. table 4. pin description ?continued symbol pin ball type description
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 15 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers p2[3]/pwm1[4]/ dcd1/ pipestat2 70 [1] e7 [1] i/o p2[3] ? general purpose digital input/output pin. o pwm1[4] ? pulse width modulator 1, channel 4 output. i dcd1 ? data carrier detect input for uart1. o pipestat2 ? pipeline status, bit 2. p2[4]/pwm1[5]/ dsr1/ tracesync 69 [1] d9 [1] i/o p2[4] ? general purpose digital input/output pin. o pwm1[5] ? pulse width modulator 1, channel 5 output. i dsr1 ? data set ready input for uart1. o tracesync ? trace synchronization. p2[5]/pwm1[6]/ dtr1/ tracepkt0 68 [1] d10 [1] i/o p2[5] ? general purpose digital input/output pin. o pwm1[6] ? pulse width modulator 1, channel 6 output. o dtr1 ? data terminal ready output for uart1. o tracepkt0 ? trace packet, bit 0. p2[6]/pcap1[0]/ ri1/ tracepkt1 67 [1] e8 [1] i/o p2[6] ? general purpose digital input/output pin. i pcap1[0] ? capture input for pwm1, channel 0. i ri1 ? ring indicator i nput for uart1. o tracepkt1 ? trace packet, bit 1. p2[7]/rd2/ rts1/ tracepkt2 66 [1] e9 [1] i/o p2[7] ? general purpose digital input/output pin. i rd2 ? can2 receiver input. (lpc2364/66/68 only) o rts1 ? request to send output for uart1. o tracepkt2 ? trace packet, bit 2. p2[8]/td2/ txd2/ tracepkt3 65 [1] e10 [1] i/o p2[8] ? general purpose digital input/output pin. o td2 ? can2 transmitter output. (lpc2364/66/68 only) o txd2 ? transmitter output for uart2. o tracepkt3 ? trace packet, bit 3. p2[9]/ usb_connect/ rxd2/extin0 64 [1] f7 [1] i/o p2[9] ? general purpose digital input/output pin. o usb_connect ? signal used to switch an external 1.5 k ? resistor under software control. used with the soft connect usb featur e. (lpc2364/66/68 only) i rxd2 ? receiver input for uart2. i extin0 ? external trigger input. p2[10]/eint0 53 [6] j10 [6] i/o p2[10] ? general purpose digital input/output pin. note: low on this pin while reset is low forces on-chip bootloader to take over control of the part after a reset. i eint0 ? external interrupt 0 input. p2[11]/eint1 / mcidat1/ i2stx_clk 52 [6] h8 [6] i/o p2[11] ? general purpose digital input/output pin. i eint1 ? external interrupt 1 input. o mcidat1 ? data line for sd/mmc interface. (lpc2367/68 only) i/o i2stx_clk ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . table 4. pin description ?continued symbol pin ball type description
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 16 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers p2[12]/eint2 / mcidat2/ i2stx_ws 51 [6] k10 [6] i/o p2[12] ? general purpose digital input/output pin. i eint2 ? external interrupt 2 input. o mcidat2 ? data line for sd/mmc interface. (lpc2367/68 only) i/o i2stx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . p2[13]/eint3 / mcidat3/ i2stx_sda 50 [6] j9 [6] i/o p2[13] ? general purpose digital input/output pin. i eint3 ? external interrupt 3 input. o mcidat3 ? data line for sd/mmc interface. (lpc2367/68 only) i/o i2stx_sda ? transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . p3[0] to p3[31] i/o port 3: port 3 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 3 pins depends upon the pin function selected via the pin connect block. pins 0 through 24, and 27 through 31 of this port are not available. p3[25]/mat0[0]/ pwm1[2] 27 [1] h3 [1] i/o p3[25] ? general purpose digital input/output pin. o mat0[0] ? match output for timer 0, channel 0. o pwm1[2] ? pulse width modulator 1, output 2. p3[26]/mat0[1]/ pwm1[3] 26 [1] k1 [1] i/o p3[26] ? general purpose digital input/output pin. o mat0[1] ? match output for timer 0, channel 1. o pwm1[3] ? pulse width modulator 1, output 3. p4[0] to p4[31] i/o port 4: port 4 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 4 pins depends upon the pin function selected via the pin connect block. pins 0 through 27, 30, and 31 of this port are not available. p4[28]/mat2[0]/ txd3 82 [1] c7 [1] i/o p4[28] ? general purpose digital input/output pin. o mat2[0] ? match output for timer 2, channel 0. o txd3 ? transmitter output for uart3. p4[29]/mat2[1]/ rxd3 85 [1] e6 [1] i/o p4[29] ? general purpose digital input/output pin. o mat2[1] ? match output for timer 2, channel 1. i rxd3 ? receiver input for uart3. dbgen - d4 [1] [8] i dbgen ? jtag interface control signal. also used for boundary scanning. note: this pin is available in lpc2364fet100 and lpc2368fet100 devices only (tfbga package). tdo 1 [1] [7] a1 [1] [7] o tdo ? test data out for jtag interface. tdi 2 [1] [8] c3 [1] [8] i tdi ? test data in for jtag interface. tms 3 [1] [8] b1 [1] [8] i tms ? test mode select for jtag interface. trst 4 [1] [8] c2 [1] [8] i trst ? test reset for jtag interface. tck 5 [1] [7] c1 [1] [7] i tck ? test clock for jtag interface. th is clock must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate rtck 100 [1] [8] b2 [1] [8] i/o rtck ? jtag interface control signal. note: low on this pin while reset is low enables etm pins (p2[9:0]) to operate as trace port after reset. table 4. pin description ?continued symbol pin ball type description
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 17 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers [1] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis. [2] 5 v tolerant pad providing digital i/o functions (with ttl levels and hysteresis) and analog input. when configured as a dac input, digital section of the pad is disabled. [3] 5 v tolerant pad providing digital i/o with ttl levels and hysteresis and analog output functi on. when configured as the dac output, digital section of the pad is disabled. [4] open-drain 5 v tolerant digital i/o pad, compatible with i 2 c-bus 400 khz specification. this pad requ ires an external pull-up to provide output functionality. when power is sw itched off, this pin connected to the i 2 c-bus is floating and does not disturb the i 2 c lines. open-drain configuration applies to all functions on this pin. [5] pad provides digital i/o and usb functions (lpc2364/66/68 only). it is designed in accordance with the usb specification, revision 2.0 (full-speed and low-speed mode only). [6] 5 v tolerant pad with 10 ns glitch filter providi ng digital i/o functions with ttl levels and hysteresis. [7] this pin has no built-in pull-up and no built-in pull-down resistor. [8] this pin has a built-in pull-up resistor. [9] 5 v tolerant pad with 20 ns glitch filter providi ng digital i/o function with ttl levels and hysteresis. [10] pad provides special analog functionality. [11] when the main oscillator is not used, connect xtal1 and xta l2 as follows: xtal1 can be left floating or can be grounded (gr ounding is preferred to reduce susceptibility to noise). xtal2 should be left floating. rstout 14 - o rstout ? this is a 3.3 v pin. low on this pin indicates lpc2364/65/66/67/68 being in reset state. note: this pin is available in lpc2364fbd100, lpc2365fbd100, lpc2366fbd100, lpc2367fbd100, and lpc2368fbd100 devices only (lqfp100 package). reset 17 [9] f3 [9] i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 22 [10] [11] h2 [10] [11] i input to the oscillator circuit and internal clock generator circuits. xtal2 23 [10] [11] g3 [10] [11] o output from the oscillator amplifier. rtcx1 16 [10] [12] f2 [10] [12] i input to the rtc oscillator circuit. rtcx2 18 [10] g1 [10] o output from the rtc oscillator circuit. v ss 15, 31, 41, 55, 72, 97, 83 [13] b3, b7, c9, f1, g7, j6, k3 [13] i ground: 0 v reference. v ssa 11 [14] e1 [14] i analog ground: 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v dd(3v3) 28, 54, 71, 96 [15] a3, c10, h9, k2 [15] i 3.3 v supply voltage: this is the power supply voltage for the i/o ports. v dd(dcdc)(3v3) 13, 42, 84 [16] a7, e4, h6 [16] i 3.3 v dc-to-dc converter supply voltage: this is the supply voltage for the on-chip dc-to-dc converter only. v dda 10 [17] e2 [17] i analog 3.3 v pad supply voltage: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. this voltage is used to power the adc and dac. vref 12 [17] e3 [17] i adc reference: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. level on this pin is used as a reference for adc and dac. vbat 19 [17] g2 [17] i rtc pin power supply: 3.3 v on this pin suppl ies the power to the rtc peripheral. table 4. pin description ?continued symbol pin ball type description
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 18 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers [12] if the rtc is not used, these pins can be left floating. [13] pad provides special analog functionality. [14] pad provides special analog functionality. [15] pad provides special analog functionality. [16] pad provides special analog functionality. [17] pad provides special analog functionality. 7. functional description 7.1 architectural overview the lpc2364/65/66/67/68 microcontrolle r consists of an arm7tdmi-s cpu with emulation support, the arm7 local bus for cl osely coupled, high-speed access to the majority of on-chip memory, the amba ahb in terfacing to high-speed on-chip peripherals, and the amba apb for connection to other on-chip peripheral functions. the microcontroller permanently configures the ar m7tdmi-s processor for little-endian byte order. the lpc2364/65/66/67/68 implements two ahb in order to allow the ethernet block to operate without interference caused by other system activity. the primary ahb, referred to as ahb1, includes the vic and gpdma controller. the second ahb, referred to as ahb2, in cludes only the ethernet block and an associated 16 kb sram. in addition, a bus bridge is provided that allows the secondary ahb to be a bus master on ahb1, allowing expansion of ethernet buffer space into off-chip memory or unused space in memory residing on ahb1. in summary, bus masters with access to ahb1 are the arm7 itself, the gpdma function, and the ethernet block (via the bus bridge from ahb2). bus masters wi th access to ahb2 are the arm7 and the ethernet block. ahb peripherals are allocated a 2 mb range of addresses at the very top of the 4 gb arm memory space. each ahb peripheral is allocated a 16 kb address space within the ahb address space. lo wer speed periph eral functions are conn ected to the apb. the ahb to apb bridge interfaces the apb to the ahb. apb periph erals are also allocated a 2 mb range of addresses, beginning at the 3.5 gb address point. each apb peripheral is allocated a 16 kb address space within the apb address space. the arm7tdmi-s processor is a general purp ose 32-bit microprocessor, which offers high performance and very low power consumption. the arm architecture is based on reduced instruction set comput er (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 19 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set ? a 16-bit thumb set the thumb set?s 16-bit instru ction length allows it to approach twice the density of standard arm code while retaining most of the arm?s performance advantage over a traditional 16-bit processor using 16-bit regist ers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm processo r connected to a 16-bit memory system. 7.2 on-chip flash programming memory the lpc2364/65/66/67/68 incorporate a 128 kb, 256 kb, and 512 kb flash memory system respectively. this memory may be used for both code and data storage. programming of the flash memory may be accomplished in several ways. it may be programmed in system via the serial port (uart0). the application program may also erase and/or program the flash while the applicat ion is running, allowing a great degree of flexibility for data storage field and firmware upgrades. the flash memory is 128 bits wide and includ es pre-fetching and buffering techniques to allow it to operate at sram speeds of 72 mhz. lpc2364hbd flash operates up to 72 mhz from ? 40 ? c to +85 ? c, up to 60 mhz from 85 ? c to 125 ? c. 7.3 on-chip sram the lpc2364/65/66/67/68 include sram memory of 8 kb or 32 kb, reserved for the arm processor exclusive use. this ram may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. a 16 kb sram block serving as a buffer fo r the ethernet controller and an 8 kb sram used by the gpdma controller or the usb de vice can be used both for data and code storage. the 2 kb rtc sram can be used for data storage only. the rtc sram is battery powered and retains the content in the absence of the main power supply. 7.4 memory map the lpc2364/65/66/67/68 memory map incorporat es several distinct regions as shown in figure 4 . in addition, the cpu interrupt vectors may be remapped to allow them to reside in either flash memory (default), boot rom, or sram (see section 7.25.6 ).
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 20 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 7.5 interrupt controller the arm processor core has two interrupt inputs called interrupt request (irq) and fast interrupt request (fiq). the vic takes 32 interrupt request inputs which can be programmed as fiq or vectored irq types. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fig 4. lpc2364/65/66/67/68 memory map 0.0 gb 1.0 gb total of 128 kb on-chip non-volatile memory (lpc2364) total of 512 kb on-chip non-volatile memory (lpc2367/68) total of 256 kb on-chip non-volatile memory (lpc2365/66) 0x0000 0000 0x0001 ffff 0x0002 0000 0x0003 ffff 0x0007 ffff 0x0008 0000 0x0004 0000 reserved for on-chip memory 8 kb local on-chip static ram (lpc2364) 32 kb local on-chip static ram (lpc2365/66/67/68) reserved address space reserved address space 0x4000 0000 0x4000 2000 0x4000 8000 0x7fd0 0000 0x7fe0 0000 0x7fd0 1fff 0x7fe0 3fff 0x4000 1fff 0x4000 7fff 2.0 gb 0x8000 0000 boot rom and boot flash (boot flash remapped from on-chip flash) 3.0 gb 0xc000 0000 reserved address space 3.75 gb 4.0 gb 3.5 gb ahb peripherals apb peripherals 0xe000 0000 0xf000 0000 0xffff ffff general purpose or usb ram (8 kb) ethernet ram (16 kb) 002aac577
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 21 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers fiqs have the highest priority. if more than one request is assigned to fiq, the vic ors the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classified as fiq, because then the fiq service routine can simply start dealing with that device. but if more than one request is assigned to the fiq class, the fiq service ro utine can read a word from the vic that identifies which fiq source(s) is (are) requesting an interrupt. vectored irqs, which include all interrupt requests that are not classified as fiqs, have a programmable interrupt priority. when more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered vic channel will be serviced first. the vic ors the requests from all of the vectored irqs to produce the irq signal to the arm processor. the irq service routine can st art by reading a register from the vic and jumping to the address supplied by that register. 7.5.1 interrupt sources each peripheral device has one interrupt line connected to the vic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. any pin on port 0 and port 2 (total of 42 pi ns) regardless of the selected function, can be programmed to generate an in terrupt on a rising edge, a fa lling edge, or both. such interrupt request coming from port 0 and/or port 2 will be combined with the eint3 interrupt requests. 7.6 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 general purpose dma controller the gpdma is an amba ahb complia nt peripheral allowing selected lpc2364/65/66/67/68 peripherals to have dma support. the gpdma enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional serial dma transfer s for a single source and destination. for example, a bidirectional port requires one st ream for transmit and one for receive. the source and destination areas can each be either a memory region or a peripheral, and can be accessed through the ahb master. 7.7.1 features ? two dma channels. each channel can support a unidirectional transfer. ? the gpdma can transfer data between the 8 kb sram and peripherals such as the sd/mmc, two ssp, and i 2 s interfaces.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 22 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers ? single dma and burst dma request signals. each peripheral connected to the gpdma can assert either a burst dma request or a single dma request. the dma burst size is set by programming the gpdma. ? memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. ? scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not hav e to occupy contiguous areas of memory. ? hardware dma chan nel priority. each dma channel has a specific hardware priority. dma channel 0 has the highest priority and channel 1 has the lowest priority. if requests from two channels become active at the same time the channel with the highest priority is serviced first. ? ahb slave dma programming interface. the gpdma is programmed by writing to the dma control registers over the ahb slave interface. ? one ahb master for transferring data. this interface transfers data when a dma request goes active. ? 32-bit ahb master bus width. ? incrementing or non-incrementing addressing for source and destination. ? programmable dma burst size. the dma burst size can be programmed to more efficiently transfer data. usually the burst size is set to half the size of the fifo in the peripheral. ? internal four-word fifo per channel. ? supports 8-bit, 16-bit, and 32-bit wide transactions. ? an interrupt to the processor can be generated on a dma completion or when a dma error has occurred. ? interrupt masking. the dma error and dma terminal count interrupt requests can be masked. ? raw interrupt status. the dma error and dma count raw interrupt status can be read prior to masking. 7.8 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically conf igured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. lpc2364/65/66/67/68 use accelerated gpio functions: ? gpio registers are relocated to the arm loca l bus so that the fa stest possible i/o timing can be achieved. ? mask registers allow treating sets of por t bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 23 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers additionally, any pin on port 0 and port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. the edge detection is asynchronous, so it may operate when clocks are not present such as during power-down mode. each enabled interrupt can be used to wake up the chip from power-down mode. 7.8.1 features ? bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. ? backward compatibility with other earlier devi ces is maintained with legacy port 0 and port 1 registers appearing at th e original addresses on the apb. 7.9 ethernet the ethernet block contains a full featur ed 10 mbit/s or 100 mbit/s ethernet mac designed to provide optimized performa nce through the use of dma hardware acceleration. features include a generous suite of control registers, half or full duplex operation, flow control, cont rol frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on lan activity. automatic frame transmission and reception with scatter-gather dma off-loads many operations from the cpu. the ethernet block and the cpu share a dedicated ahb subsystem that is used to access the ethernet sram for ethernet data, control, and status information. all other ahb traffic in the lpc2364/65/66/67/68 takes place on a different ahb subsystem, effectively separating ethernet activity from the rest of the system. the ethernet dma can also access the usb sram if it is not being used by the usb block. the ethernet block interfaces between an off-chip ethernet phy using the reduced mii (rmii) protocol and the on-chip media independent interface management (miim) serial bus. 7.9.1 features ? ethernet standards support: ? supports 10 mbit/s or 100 mbit/s phy dev ices including 10 base-t, 100 base-tx, 100 base-fx, and 100 base-t4. ? fully compliant with ieee standard 802.3 . ? fully compliant with 802.3x full duplex fl ow control and half duplex back pressure. ? flexible transmit and receive frame options. ? virtual local area network (vlan) frame support. ? memory management: ? independent transmit and receive buffers memory mapped to shared sram. ? dma managers with scatter/gather dma and arrays of frame descriptors. ? memory traffic optimized by buffering and pre-fetching. ? enhanced ethernet features:
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 24 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers ? receive filtering. ? multicast and broadcast frame support for both transmit and receive. ? optional automatic frame check sequence (fcs) insertion with circular redundancy check (crc) for transmit. ? selectable automatic transmit frame padding. ? over-length frame support for both transmit and receive allows any length frames. ? promiscuous receive mode. ? automatic collision back-off and frame retr ansmission. ? includes power management by clock switching. ? wake-on-lan power management support allows system wake-up: using the receive filters or a magic frame detection filter. ? physical interface: ? attachment of external phy chip through standard rmii interface. ? phy register access is available via the miim interface. 7.10 usb interface (lpc2364/66/68 only) the universal serial bu s (usb) is a 4-wire bus that supports communication between a host and a number (127 maximum) of peripherals. the host controller allocates the usb bandwidth to attached devices through a token based protocol. the bus supports hot plugging, unplugging, and dynamic configurat ion of the devices. all transactions are initiated by the host controller. 7.10.1 usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of register interface, serial interface engine, endpoint buffer memory, and the dma controller. the serial interface engine dec odes the usb data stream and writes data to the appropriate end point buffer memory. the status of a completed usb transfer or error condition is indicated via status register s. an interrupt is also generated if enabled. the dma controller when enabled transfers data between the endpoint buffer and the usb ram. 7.10.2 features ? fully compliant with usb 2.0 specification (full speed). ? supports 32 physical (16 logical) endpoints with a 4 kb usb endpoint buffer ram. ? supports control, bulk, interrupt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum specification) by software at run time. ? supports softconnect and goodlink features. ? while usb is in the suspend mode, lpc2364/65/66/67/68 can enter one of the reduced power modes and wake up on a usb activity. ? supports dma transfers with the dma ram of 8 kb on all non-control endpoints. ? allows dynamic switching betwee n cpu-controlled and dma modes.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 25 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers ? double buffer implementation for bulk and isochronous endpoints. 7.11 can controller and acceptan ce filters (lpc2364/66/68 only) the controller area network (can) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. its domain of application ranges from high-speed ne tworks to low cost multiplex wiring. the can block is intended to support multip le can buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of can buses in industrial or automotive applications. each can controller has a regi ster structure sim ilar to the nxp sja1 000 and the pelican library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the arm environment. the main operational difference is that the recognition of received identifiers, known in can terminology as acceptance filtering, has been removed from the can controllers and centralized in a global acceptance filter. 7.11.1 features ? two can controllers and buses. ? data rates to 1 mbit/s on each bus. ? 32-bit register and ram access. ? compatible with can specification 2.0b, iso 11898-1 . ? global acceptance filter recognizes 11-bit and 29-bit receive identifiers for all can buses. ? acceptance filter can provide fullcan-s tyle automatic reception for selected standard identifiers. ? fullcan messages can gen erate interrupts. 7.12 10-bit adc the lpc2364/65/66/67/68 contain one ad c. it is a single 10-bit successive approximation adc with six channels. 7.12.1 features ? 10-bit successive approximation adc. ? input multiplexing among 6 pins. ? power-down mode. ? measurement range 0 v to v i(vref) . ? 10-bit conversion time ? 2.44 ? s. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 26 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 7.13 10-bit dac the dac allows the lpc2364/65/66/67/68 to generate a variable analog output. the maximum output value of the dac is v i(vref) . 7.13.1 features ? 10-bit dac ? resistor string architecture ? buffered output ? power-down mode ? selectable output drive 7.14 uarts the lpc2364/65/66/67/68 each contain four ua rts. in addition to standard transmit and receive data lines, uart1 also provides a full modem control handshake interface. the uarts include a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.14.1 features ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? uart1 equipped with standard modem interface signals. this module also provides full support for hardware flow control (auto-cts/rts). ? uart3 includes an irda mode to support infrared communication. 7.15 spi serial i/o controller the lpc2364/65/66/67/68 each contain one spi controller. spi is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.15.1 features ? compliant with spi specification ? synchronous, serial, full duplex communication ? combined spi master and slave ? maximum data bit rate of one eighth of the input clock rate ? 8 bits to 16 bits per transfer
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 27 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 7.16 ssp serial i/o controller the lpc2364/65/6 6/67/68 each contain two ssp co ntrollers. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.16.1 features ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame ? dma transfers supported by gpdma 7.17 sd/mmc card interface (lpc2367/68 only) the secure digital and multimed ia card interface (mci) allows access to external sd memory cards. the sd card interface conforms to the sd multimedia ca rd specification version 2.11 . 7.17.1 features ? the mci interface provides all functions sp ecific to the sd/mmc memory card. these include the clock generation unit, power management control, and command and data transfer. ? conforms to multimedia card specification v2.11 . ? conforms to secure digital memory card phys ical layer specification, v0.96. ? can be used as a multimedia card bus or a secure digital memory card bus host. the sd/mmc can be connected to several multimedia cards or a single secure digital memory card. ? dma supported through the gpdma controller. 7.18 i 2 c-bus serial i/o controllers the lpc2364/65/66/67/68 each contain three i 2 c-bus controllers. the i 2 c-bus is bidirectional, for inter-ic contro l using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus, it can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in lpc2364/65/66/67/68 supports bit rates up to 400 kbit/s (fast i 2 c-bus).
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 28 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 7.18.1 features ? i 2 c0 is a standard i 2 c compliant bus interface with open-drain pins. ? i 2 c1 and i 2 c2 use standard i/o pins and do not support powering off of individual devices connected to the same bus lines. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. 7.19 i 2 s-bus serial i/o controllers the i 2 s-bus provides a standard communication interface for digital audio applications. the i 2 s-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. the basic i 2 s connection has one master, which is always the master, and one slave. the i 2 s interface on the lpc2364/65/66/67/68 provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.19.1 features ? the interface has separate input/output chan nels each of which can operate in master or slave mode. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? the sampling frequency can range from 16 khz to 48 khz (16, 22.05, 32, 44.1, 48) khz. ? configurable word select period in master mode (separately for i 2 s input and output). ? two 8-word fifo data buffers are provided, one for transmit and one for receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests, controlled by programma ble buffer levels. these are connected to the gpdma block. ? controls include reset, stop and mute options separately for i 2 s input and i 2 s output.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 29 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 7.20 general purpose 32-bit time rs/external event counters the lpc2364/65/66/67/68 include four 32-b it timer/counters. the timer/counter is designed to count cycles of the system derive d clock or an externally-supplied clock. it can optionally generate interrupts or perf orm other actions at specified timer values, based on four match registers. the timer/count er also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.20.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. 7.21 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on th e lpc2364/65/66/67/68. the timer is designed to count cycles of the system derived clock and op tionally switch pins, generate in terrupts or perform other actions when specified ti mer values occur, based on seven match registers. the pwm function is in addition to these features, and is based on match register events. the ability to separately contro l rising and falling edge locations allo ws the pwm to be used for more applications. for instance, mu lti-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. one match register (pwmmr0) controls the pwm cycle rate, by resetting the count upon match. the other match register controls th e pwm edge position. additional single edge controlled pwm outputs require only one match re gister each, since the repetition rate is the same for all pwm outputs. multiple single edge contro lled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an pwmmr0 match occurs.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 30 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers three match registers can be used to provid e a pwm output with both edges controlled. again, the pwmmr0 match register contro ls the pwm cycle rate. the other match registers control the two pwm edge positi ons. additional double edge controlled pwm outputs require only two match registers each, si nce the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, spec ific match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative goi ng pwm pulses (when the falling edge occurs prior to the rising edge). 7.21.1 features ? lpc2364/65/66/67/68 has one pwm block with counter or timer operation (may use the peripheral clock or one of the capture inputs as the clock source). ? seven match registers allow up to six single edge controlled or three double edge controlled pwm outputs, or a mix of bot h types. the match registers also allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this a llows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete flexibility in the trad e-off between resolution and re petition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses. ? match register updates are synchronized wit h pulse outputs to prevent generation of erroneous pulses. software must ?release? new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32-bit timer/counter with a programmable 32-bit prescaler. 7.22 watchdog timer the purpose of the watchdog is to reset the mi crocontroller within a reasonable amount of time if it enters an erroneous state. when enabl ed, the watchdog w ill generate a system reset if the user program fails to ?feed? (o r reload) the watchdog within a predetermined amount of time. 7.22.1 features ? internally resets chip if not period ically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 31 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 32 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the rtc clock, the internal rc oscillator (irc), or the apb peripheral clock. this gives a wide range of potential timing choices of watchdog o peration under different power reduction conditions. it also provides the ability to run the wdt from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for incr eased reliability. 7.23 rtc and battery ram the rtc is a set of counters for measuring ti me when system power is on, and optionally when it is off. it uses little power in power-down and deep power-down modes. on the lpc2364/65/66/67/68 , the rtc can be clocked by a sepa rate 32.768 khz oscillator, or by a programmable prescale divider based on the apb clock. also, the rtc is powered by its own power supply pin, vbat, which can be connected to a battery or to the same 3.3 v supply used by the rest of the device. the vbat pin supplies power only to the rtc and the battery ram. these two functions require a minimum of power to operate, whic h can be supplied by an external battery. 7.23.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? dedicated 32 khz oscillator or prog rammable prescale r from apb clock. ? dedicated power supply pin can be connected to a battery or to the main 3.3 v. ? periodic interrupts can be generated from in crements of any field of the time registers, and selected fractional second values. ? 2 kb data sram powered by vbat. ? rtc and battery ram power supply is isolated from the rest of the chip. 7.24 clocking and power control 7.24.1 crystal oscillators the lpc2364/65/66/ 67/68 includes three independent osc illators. these are the main oscillator, the internal rc o scillator, and the rtc oscillator. each oscillator can be used for more than one purpose as required in a particular application. any of the three clock sources can be chosen by software to drive the pll and ultimately the cpu. following reset, the lpc2364/65 /66/67/68 will operate from the internal rc oscillator until switched by software. this a llows systems to operate without any external crystal and the bootloader code to operate at a known frequency.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 32 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 7.24.1.1 internal rc oscillator the irc may be used as the clock source for th e wdt, and/or as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 4 mhz. the irc is trimmed to ? 1 % accuracy. upon power-up or any chip reset, the lpc2 364/65/66/67/68 uses the irc as the clock source. software may later switch to one of the other available clock sources. 7.24.1.2 main oscillator the main oscillator can be used as the clock so urce for the cpu, with or without using the pll. the main oscillato r operates at freq uencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the pll. the clock selected as the pll inpu t is pllclkin. the arm processor clock frequency is referred to as cclk elsewhere in this document. the frequencies of pllclkin and cclk are the same value unless the pll is active and connected. the clock frequency for each peripheral can be selected individually and is referred to as pclk. refer to section 7.24.2 for additional information. 7.24.1.3 rtc oscillator the rtc oscillator can be used as the clock so urce for the rtc and/or the wdt. also, the rtc oscillator can be used to drive the pll and the cpu. 7.24.2 pll the pll accepts an input clock frequency in the range of 32 khz to 50 mhz. the input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the cpu and the usb block. th e usb block is available in lpc2364/66/68 only. the pll input, in the range of 32 khz to 50 mhz, may initially be divided down by a value ?n?, which may be in the range of 1 to 256. this input divi sion provides a wide range of output frequencies from the same input frequency. following the pll input divider is the pll mult iplier. this can multiply the input divider output through th e use of a current controlled oscilla tor (cco) by a value ?m?, in the range of 1 through 32768. the resulting frequency must be in the range of 275 mhz to 550 mhz. the multiplier works by dividing the cco output by the value of m, then using a phase-frequency detector to compare the divided cco output to the multiplier input. the error value is used to adjust the cco frequency. the pll is turned off and bypassed following a chip reset and by entering power-down mode. pll is enabled by software only. the pr ogram must configure and activate the pll, wait for the pll to lock, then connect to the pll as a clock source. 7.24.3 wake-up timer the lpc2364/65/66/67/68 begins operati on at power-up and when awakened from power-down and deep power-down modes by using the 4 mhz irc oscillator as the clock source. this allows chip operati on to resume quickly. if the main oscillator or the pll is needed by the application, soft ware will need to enable thes e features and wait for them to stabilize before they ar e used as a clock source.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 33 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers when the main oscillator is init ially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. this is im portant at power on, all types of reset, and whenever any of the aforemen tioned functions are turned off for any reason. since the oscillator and other function s are turned off during powe r-down and deep-power down modes, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. when power is applied to th e chip, or when some event caused the chip to exit power-down mode , some time is requir ed for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd(3v3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.24.4 power control the lpc2364/65/66/67/68 supports a variety of power control features. there are four special modes of processor power reduction: idle mode, sleep mode, power-down mode, and deep power-down mode. the cpu clock ra te may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power ve rsus processing speed based on application requirements. in addition, peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. each of the peripherals has its own clock divider wh ich provides even better power control. the lpc2364/65/66/67/68 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the rtc and a small sram, refe rred to as th e battery ram. 7.24.4.1 idle mode in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.24.4.2 sleep mode in sleep mode, the oscillator is shut down an d the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout sleep mode and the logic levels of chip pins remain static. the output of the irc is disabled but the irc is not powered down for a fast wake-up later. the 32 khz rtc oscillator is not stopped becaus e the rtc interrupts may be used as the wake-up source. the pll is automatically turned off and disconnected. the cclk and usb clock dividers automati cally get reset to zero. the sleep mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, sleep mode reduces chip power consumption to a very low value. the flash memo ry is left on in sleep mode, allowing a very quick wake-up.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 34 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers on the wake-up of sleep mode, if the irc was used before entering sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. if the main external oscillator was used, the code exec ution will resume when 4096 cycles expire. the customers need to reconfigure the pll and clock dividers accordingly. 7.24.4.3 power-down mode power-down mode does everyt hing that sleep mode does, but also turns off the irc oscillator and the flash memory. this save s more power, but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. on the wake-up of power-down mode, if the irc was used before entering power-down mode, it will take irc 60 ? s to start-up. after this 4 irc cycles will expire before the code execution can then be resumed if the code was running from sram. in the meantime, the flash wake-up timer then counts 4 mhz irc clock cycles to make the 100 ? s flash start-up time. when it times out, access to the flash will be allowed. the customers need to reconfigure the pll and clock dividers accordingly. 7.24.4.4 deep power-down mode deep power-down mode is similar to the power-down mode, but now the on-chip regulator that supplies power to the internal logic is also shut off. this produces the lowest possible power consum ption without removing power from the entire chip. since the deep power-down mode shuts down the on-chip logic power supply, there is no register or memory retention, and resumption of operation involves the same activities as a full chip reset. if power is supplied to the lpc2364/65/66/67/68 during deep power-down mode, wake-up can be caused by the rtc alarm interrupt or by external reset. while in deep power-down mode, external device power may be removed. in this case, the lpc2364/65/66/67/68 will start up when external power is restored. essential data may be retained through deep power-down mode (or through complete powering off of the chip) by storing data in t he battery ram, as long as the external power to the vbat pin is maintained. 7.24.4.5 power domains the lpc2364/65/66/67/68 provides two indepen dent power domains th at allow the bulk of the device to have power removed while maintaining operation of the rtc and the battery ram. on the lpc2364/65/66/67/68, i/o pads are powered by the 3.3 v (v dd(3v3) ) pins, while the v dd(dcdc)(3v3) pin powers the on-chip dc-to-dc converter which in turn provides power to the cpu and most of the peripherals. depending on the lpc2364/65/66/67/68 applic ation, a design can use two power options to manage power consumption.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 35 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers the first option assumes that power consumptio n is not a concern and the design ties the v dd(3v3) and v dd(dcdc)(3v3) pins together. this approach requires only one 3.3 v power supply for both pads, the cpu, and peripherals. while this solution is simple, it does not support powering down the i/o pad ring ?on the fly? while keeping the cpu and peripherals alive. the second option uses two power supplie s; a 3.3 v supply for the i/o pads (v dd(3v3) ) and a dedicated 3.3 v supply for the cpu (v dd(dcdc)(3v3) ). having the on-chip dc-to-dc converter powered independently from the i/o pad ring enables shutting down of the i/o pad power supply ?on the fly?, while the cpu and peripherals stay active. the vbat pin supplies power only to the rtc and the battery ram. these two functions require a minimum of power to operate, whic h can be supplied by an external battery. when the cpu and the rest of chip functi ons are stopped and power removed, the rtc can supply an alarm output that may be used by external hardware to restore chip power and resume operation. 7.25 system control 7.25.1 reset reset has four source s on the lpc2364/65 /66/67/68: the reset pin, the watchdog reset, power-on reset, and the browno ut detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in section 7.24.3 ? wake-up timer ? ), causing reset to re main asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has complete d its initialization. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector ma pped from the boot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. 7.25.2 brownout detection the lpc2364/65/66/67/68 includes 2-stage monitoring of the voltage on the v dd(dcdc)(3v3) pins. if this voltage falls below 2.95 v, the bod asserts an interrupt signal to the vectored interrupt controller. this signal can be enabled for interrupt in the interrupt enable register in the vic in order to cause a cpu interrupt; if not, software can monitor the signal by reading a dedicated status register. the second stage of low-voltage detection asserts reset to inactivate the lpc2364/65/66/67/68 when the voltage on the v dd(dcdc)(3v3) pins falls below 2.65 v. this reset prevents alteration of the flash as oper ation of the various elements of the chip would otherwise become unreliable due to low voltage. the bod circ uit maintains this reset down below 1 v, at which point the power-on reset circuitry maintains the overall reset. both the 2.95 v and 2.65 v thresholds include some hysteresis. in normal operation, this hysteresis allows the 2.95 v de tection to reliably interrupt, or a regularly executed event loop to sense the condition.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 36 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 7.25.3 code security (code read protection - crp) this feature of the lpc2364/65/66/67/68 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the jtag and isp can be restricted. when needed, crp is invoked by programming a specific pattern into a dedicated flash location. iap commands are not affected by the crp. there are three levels of the code read protection. crp1 disables access to chip via the jtag and allows partial flash update (excluding flash sector 0) using a limited set of the is p commands. this mode is useful when crp is required and flash field updates are needed but all sectors can not be erased. crp2 disables access to chip via the jtag and only allows full flash erase and update using a reduced set of the isp commands. running an application with level crp3 selected fully disa bles any access to chip via the jtag pins and the isp. this mode effectively disables isp override using p2[10] pin, too. it is up to the user?s application to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via uart0. 7.25.4 ahb the lpc2364/65/66/67/68 implement two ahbs in order to allow the ethernet block to operate without interference caused by other system activity. the primary ahb, referred to as ahb1, includes the vect ored interrupt controller, gpdma contro ller, usb interface, and 8 kb sram primarily intended for use by the usb. the usb interface is available on lpc2364/66/68 only. the second ahb, referred to as ahb2, in cludes only the ethernet block and an associated 16 kb sram. in addition, a bus bridge is provided that allows the secondary ahb to be a bus master on ahb1, allowing expansion of ethernet buffer space into unused space in memory residing on ahb1. in summary, bus masters with access to ahb1 are the arm7 itself, the usb block, the gpdma function, and the etherne t block (via the bus bridge from ahb2). bus masters with access to ahb2 are the arm7 and the ethernet block. 7.25.5 external interrupt inputs the lpc2364/65/66/67/68 include up to 46 ed ge sensitive interrupt inputs combined with up to four level sensitive exte rnal interrupt inputs as selectable pin functions. the external interrupt inputs can optionally be used to wake up the processor from power-down mode. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 37 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 7.25.6 memory mapping control the memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. vectors may be mapped to the bottom of the boot rom or the sram. this allows code running in different memory spaces to have control of the interrupts. 7.26 emulation and debugging the lpc2364/65/66/67/68 supp ort emulation and debugging via a jtag serial port. a trace port allows tracing program execution. debugging and trace functions are multiplexed only with gpios on p2[0] to p2[9]. this mean s that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the applicat ion is run in the embedded system itself. 7.26.1 embeddedice the embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol convertor. the embeddedice protocol convertor converts the remote debug protocol commands to the jtag data needed to access the arm7tdmi-s core present on the target system. the arm core has a debug co mmunication channel (dcc) fu nction built-in. the dcc allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. the dcc is accessed as a coprocessor 14 by t he program running on the arm7tdmi-s core. the dcc allows the jtag port to be used for sending and receiving data without affecting the normal program flow. the dcc data and control registers are mapped in to addresses in the embeddedice logic. the jtag clock (tck) must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. 7.26.2 embedded trace since the lpc2364/65/66/67/68 ha ve significant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins. the etm provides real-t ime trace capability for deeply embedded processor cores. it outputs information about processor execution to a trace port. a software debugger allows configuration of th e etm using a jtag interface and displays the trace information that has been captured. the etm is connected directly to the arm core and not to the main amba system bus. it compresses the trace information and exports it through a narrow trace port. an external trace port analyzer captures the trace information under software debugger control. the trace port can broadcast the instruction trace in formation. instruction trace (or pc trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. instruction trace is significan tly compressed by only broadcasting branch addresses as well as a set of status signals th at indicate the pipeline status on a cycle by cycle basis. trace information generation can be controlled by selecting the trigger resource. trigger resources include address comparators, counters and sequencers.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 38 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers since trace information is compressed the software debugger requires a static image of the code being executed. self-modifying code can not be traced because of this restriction. 7.26.3 realmonitor realmonitor is a configurable software module, developed by arm inc., which enables real-time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communi cates with the host using the dcc, which is present in the embeddedice logic. the lpc2364/65/66/67/68 co ntain a specific configuration of realmonitor software programmed into the on-chip rom memory.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 39 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] not to exceed 4.6 v. [4] the peak current is limited to 25 times the corresponding maximum current. [5] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on required shelf lifetime. please refer to t he jedec spec (j-std-033b.1) for further details. [6] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) core and external rail 3.0 3.6 v v dd(dcdc)(3v3) dc-to-dc converter supply voltage (3.3 v) 3.0 3.6 v v dda analog 3.3 v pad supply voltage ? 0.5 +4.6 v v i(vbat) input voltage on pin vbat for the rtc ? 0.5 +4.6 v v i(vref) input voltage on pin vref ? 0.5 +4.6 v v ia analog input voltage on adc related pins ? 0.5 +5.1 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(3v3) supply voltage is present [2] ? 0.5 +6.0 v other i/o pins [2] [3] ? 0.5 v dd(3v3) + 0.5 v i dd supply current per supply pin [4] - 100 ma i ss ground current per ground pin [4] - 100 ma t stg storage temperat ure non-operating [5] ? 65 +150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [6] ? 2500 +2500 v
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 40 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 9. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. t j t amb p d r th j a ? ?? ? ?? += table 6. thermal characteristics v dd = 3.0 v to 3.6 v; t amb = ? ? ? symbol parameter conditions min typ max unit t j(max) maximum junction temperature --125 ? c table 7. thermal resistance value (c/w): 15 % v dd = 3.0 v to 3.6 v; t amb = ? ? ? lqfp100 TFBGA100 ? ja ? ja jedec (4.5 in ? 4 in) jedec (4.5 in ? 4 in) 0 m/s 37.3 0 m/s 53.9 1 m/s 32.2 1 m/s 45.5 2.5 m/s 29.5 2.5 m/s 39.5 single-layer (4.5 in ? 3 in) 8-layer (4.5 in ? 3 in) 0 m/s 54.4 0 m/s 44.3 1 m/s 42.9 1 m/s 39.2 2.5 m/s 38.8 2.5 m/s 34.2 ? jc 6.7 ? jc 9.4 ? jb 12 ? jb 10.8
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 41 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 10. static characteristics table 8. static characteristics t amb = ? 40 ? c to +85 ? c for standard devices, ? 40 ? c to +125 ? c for lpc2364hbd only, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd(3v3) supply voltage (3.3 v) core and external rail 3.0 3.3 3.6 v v dd(dcdc)(3v3) dc-to-dc converter supply voltage (3.3 v) 3.0 3.3 3.6 v v dda analog 3.3 v pad supply voltage 3.0 3.3 3.6 v v i(vbat) input voltage on pin vbat [2] 2.0 3.3 3.6 v v i(vref) input voltage on pin vref 2.5 3.3 v dda v i dd(dcdc)act(3v3) active mode dc-to-dc converter supply current (3.3 v) v dd(dcdc)(3v3) =3.3v; t amb =25 ?c; code while(1){} executed from flash; no peripherals enabled; pclk = cclk cclk = 10 mhz - 15 - ma cclk = 72 mhz - 63 - ma all peripherals enabled; pclk = cclk / 8 cclk = 10 mhz - 21 - ma cclk = 72 mhz - 92 - ma all peripherals enabled; pclk = cclk cclk = 10 mhz - 27 - ma cclk = 72 mhz - 125 - ma i dd(dcdc)pd(3v3) power-down mode dc-to-dc converter supply current (3.3 v) v dd(dcdc)(3v3) = 3.3 v; t amb =25 ?c [3] -1 1 3- ? a i dd(dcdc)dpd(3v3) deep power-down mode dc-to-dc converter supply current (3.3 v) [3] -2 0- ? a i batact active mode battery supply current [4] -2 0- ? a i bat battery supply current deep power-down mode [3] -2 0- ? a standard port pins, reset , rtck i il low-level input current v i = 0 v; no pull-up - - 3 ? a i ih high-level input current v i =v dd(3v3) ; no pull-down -- 3 ? a i oz off-state output current v o =0v; v o =v dd(3v3) ; no pull-up/down -- 3 ? a
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 42 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers i latch i/o latch-up current ? (0.5v dd(3v3) ) < v i < (1.5v dd(3v3) ); t j < 125 ?c -- 1 0 0m a v i input voltage pin configured to provide a digital function [5] [6] [7] [8] 0- 5 . 5v v o output voltage output active 0 - v dd(3v3) v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage i oh = ? 4 ma [9] v dd(3v3) ? 0.4 --v v ol low-level output voltage i ol = ? 4 ma [9] -- 0 . 4v i oh high-level output current v oh =v dd(3v3) ? 0.4 v [9] ? 4- - ma i ol low-level output current v ol =0.4v [9] 4- - m a i ohs high-level short-circuit output current v oh =0v [10] -- ? 45 ma i ols low-level short-circuit output current v ol =v dda [10] -- 5 0m a i pd pull-down current v i =5v [11] 10 50 150 ? a i pu pull-up current v i =0v; ? 40 ? c to +85 ?c ? 15 ? 50 ? 85 ? a v i =0v; > 85 ?c [12] ? 15 ? 50 ? 100 ? a v dd(3v3) lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 43 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the rtc typically fails when v i(vbat) drops below 1.6 v. [3] v dd(dcdc)(3v3) = 3.3 v; v dd(3v3) = 3.3 v; v i(vbat) = 3.3 v; t amb =25 ? c. [4] on pin vbat. [5] including voltage on outputs in 3-state mode. [6] v dd(3v3) supply voltages must be present. [7] 3-state outputs go into 3-state mode when v dd(3v3) is grounded. [8] please also see the errata note in errata sheet. [9] accounts for 100 mv voltage drop in all supply lines. [10] allowed as long as the current limit does not exceed the maximum current allowed by the device. [11] minimum condition for v i = 4.5 v, maximum condition for v i =5.5v. [12] lpc2364hbd only. [13] to v ss . [14] includes external resistors of 33 ?? 1 % on d+ and d ? . usb pins (lpc2364/66/68 only) i oz off-state output current 0v lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 44 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 10.1 power-down mode v i(vbat) = v dd(dcdc)(3v3) = 3.3 v; t amb =25 ? c. fig 5. i/o maximum supply current i dd(io) versus temperature in power-down mode v dd(3v3) = v dd(dcdc)(3v3) = 3.3 v; t amb =25 ? c. fig 6. rtc battery maximum supply current i bat versus temperature in power-down mode 002aae049 ?2 2 0 4 i dd(io) (a) ?4 temperature ( c) ?40 85 35 10 60 ?15 v dd(3v3) = 3.3 v v dd(3v3) = 3.0 v 002aae050 v i(vbat) = 3.3 v v i(vbat) = 3.0 v 10 30 20 40 i bat (a) 0 temperature ( c) ?40 85 35 10 60 ?15
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 45 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 10.2 deep power-down mode v dd(3v3) = v i(vbat) = 3.3 v; t amb =25 ? c. fig 7. total dc-to-dc converter supply current i dd(dcdc)pd(3v3) at different temperatures in power-down mode 002aae051 200 600 400 800 0 temperature ( c) ?40 85 35 10 60 ?15 v dd(dcdc)(3v3) = 3.3 v v dd(dcdc)(3v3) = 3.0 v i dd(dcdc)pd(3v3) (a) v dd(3v3) = v dd(dcdc)(3v3) = 3.3 v; t amb =25 ? c. fig 8. i/o maximum supply current i dd(io) versus temperature in deep power-down mode temperature ( c) ?40 85 35 10 60 ?15 002aae046 100 200 300 i dd(io) (a) 0 v dd(3v3) = 3.3 v v dd(3v3) = 3.0 v
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 46 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers v dd(3v3) = v dd(dcdc)(3v3) = 3.3 v; t amb =25 ? c fig 9. rtc battery maximum supply current i bat versus temperature in deep power-down mode v dd(3v3) = v i(vbat) = 3.3 v; t amb =25 ? c. fig 10. total dc-to-dc converter maximum supply current i dd(dcdc)dpd(3v3) versus temperature in deep power-down mode 002aae047 10 30 20 40 i bat (a) 0 temperature ( c) ?40 85 35 10 60 ?15 v i(vbat) = 3.3 v v i(vbat) = 3.0 v 002aae048 temperature ( c) ?40 85 35 10 60 ?15 i dd(dcdc)dpd(3v3) (a) 40 80 20 60 100 0 v dd(dcdc)(3v3) = 3.3 v v dd(dcdc)(3v3) = 3.0 v
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 47 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 10.3 electrical pi n characteristics conditions: v dd(3v3) = 3.3 v; standard port pins. fig 11. typical high-level output voltage v oh versus high-level output source current i oh conditions: v dd(3v3) = 3.3 v; standard port pins. fig 12. typical low-l evel output current i ol versus low-level output voltage v ol i oh (ma) 0 24 16 8 002aaf112 2.8 2.4 3.2 3.6 v oh (v) 2.0 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aaf111 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 48 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 11. dynamic characteristics [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [3] lpc2364hbd only. [4] bus capacitance c b in pf, from 10 pf to 400 pf. table 9. dynamic characteristics t amb = ? 40 ? c to +85 ? c for standard devices, ? 40 ? c to +125 ? c for lpc2364hbd only, unless otherwise specified; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit arm processor clock frequency f oper operating frequency cclk; ? 40 ? c to +85 ? c1 - 72 mhz cclk; > 85 ?c [3] 1-6 0m h z irc; ? 40 ? c to +85 ? c 3.96 4 4.04 mhz irc; > 85 ?c [3] 3.98 4.02 4.06 mhz external clock f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4 - - ns t clcx clock low time t cy(clk) ? 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns i 2 c-bus pins (p0[27] and p0[28]) t f(o) output fall time v ih to v il 20 + 0.1 ? c b [4] --ns ssp interface t su(spi_miso) spi_miso set-up time t amb = 25 ? c; measured in spi master mode; see figure 15 -1 1-n s fig 13. external clock timing (wit h an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 49 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 11.1 internal oscillators [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. 11.2 i/o pins [1] applies to standard i/o pins and reset pin. 11.3 usb interface [1] characterized but not implemented as production test. guaranteed by design. table 10. dynamic characteristic: internal oscillators t amb = ? 40 ? c to +85 ? c; 3.0 v ? v dd(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 3.96 4.02 4.04 mhz f i(rtc) rtc input frequency - - 32.768 - khz table 11. dynamic characteristic: i/o pins [1] t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 12. dynamic characteristics of us b pins (full-speed) (lpc2364/66/68 only) c l = 50 pf; r pu = 1.5 k ? on d+ to v dd(3v3) , unless otherwise specified. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 8.5 - 13.8 ns t f fall time 10 % to 90 % 7.7 - 13.7 ns t frfm differential rise and fall time matching t r /t f --1 0 9% v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 14 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 14 ? 2-+5ns t jr1 receiver jitter to next transition ? 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % ? 9-+9ns t eopr1 eop width at receiver must reject as eop; see figure 14 [1] 40 --ns t eopr2 eop width at receiver must accept as eop; see figure 14 [1] 82 --ns
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 50 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 11.4 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to t he flash. data must be written to the flash in blocks of 256 bytes. table 13. dynamic characteristics of flash t amb = ? 40 ? c to +85 ? c for standard devices, ? 40 ? c to +125 ? c for lpc2364hbd only, unless otherwise specified; v dd(3v3) = 3.0 v to 3.6 v; all voltages are measured with respect to ground. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered; ?? 100 cycles 10 - - years unpowered; ? 100 cycles 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 51 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 11.5 timing fig 14. differential da ta-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop fig 15. miso line set-up time in ssp master mode t su(spi_miso) sck shifting edges mosi miso 002aad326 sampling edges
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 52 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 12. adc electrical characteristics [1] conditions: v ssa =0v, v dda =3.3v. [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 16 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 16 . [5] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 16 . [6] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 16 . [7] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 16 . [8] see figure 17 . table 14. adc characteristics v dda = 2.5 v to 3.6 v; t amb = ? 40 ? c to +85 ? c, unless otherwise specifi ed; adc frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] [3] --? 1lsb e l(adj) integral non-linearity [1] [4] --? 2lsb e o offset error [1] [5] --? 3lsb e g gain error [1] [6] --? 0.5 % e t absolute error [1] [7] --? 4lsb r vsi voltage source interface resistance [8] --4 0k ?
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 53 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 16. adc characteristics 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out offset error e o gain error e g offset error e o v ia (lsb ideal ) 002aae604 v i(vref) ? v ssa 1024 1 lsb =
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 54 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers fig 17. suggested adc interface - lpc2364/65/66/67/68 ad0[y] pin lpc23xx ad0[y] sample ad0[y] 20 k 3 pf 5 pf r vsi v ss v ext 002aac610
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 55 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 13. dac electrical characteristics 14. application information 14.1 suggested usb interface so lutions (lpc2364/66/68 only) table 15. dac electrical characteristics v dda = 3.0 v to 3.6 v; t amb = ? 40 ? c to +85 ? c unless otherwise specified symbol parameter conditions min typ max unit e d differential linearity error - ? 1- lsb e l(adj) integral non-linearity - ? 1.5 - lsb e o offset error - 0.6 - % e g gain error - 0.6 - % c l load capacitance - 200 - pf r l load resistance 1 - - k ? fig 18. lpc2364/66/68 usb interfa ce on a self-powered device lpc23xx usb-b connector usb_d+ usb_connect softconnect switch usb_d? v bus v ss v dd(3v3) r1 1.5 k r s = 33 002aac578 r s = 33 usb_up_led
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 56 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 14.2 crystal oscillator xtal input and component selection the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i / (c i + c g ). in slave mode, a minimum of 200 mv (rms) is needed. in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 20 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtal2 pin in this configurat ion can be left unconnected. external components and models used in oscillation mode are shown in figure 21 and in ta b l e 1 6 and ta b l e 1 7 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 21 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer. fig 19. lpc2364/66/68 usb interface on a bus-powered device lpc23xx v dd(3v3) r1 1.5 k r2 usb_up_led 002aac579 usb-b connector usb_d+ usb_d? v bus v ss r s = 33 r s = 33 fig 20. slave mode operation of the on-chip oscillator lpc2xxx xtal1 c i 100 pf c g 002aae718
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 57 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers fig 21. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 16. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters): low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 /c x2 1 mhz to 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz to 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz to 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz to 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 17. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters): high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz to 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz to 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf 002aag469 lpc2xxx xtal1 xtal2 c x2 c x1 xtal = c l c p r s l
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 58 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 14.3 rtc 32 khz oscillat or component selection the rtc external oscillator circuit is shown in figure 22 . since the feedback resistance is integrated on chip, only a crystal, the capacitances c x1 and c x2 need to be connected externally to the microcontroller. ta b l e 1 8 gives the crystal parameters that should be used. c l is the typical load capacitance of the crystal and is usually specified by the crystal manufacturer. the actual c l influences oscillation freq uency. when using a crystal that is manufactured for a different load capacitance, the circuit will os cillate at a slightly different frequency (depending on the quality of the crystal) comp ared to the specified one. therefore for an accurate time reference it is advised to use the load capacitors as specified in ta b l e 1 8 that belong to a specific c l . the value of external capacitances c x1 and c x2 specified in this table are calculated from the internal parasitic capacitances and the c l . parasitics from pcb and package are not taken into account. 14.4 xtal and rtcx printed circui t board (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. fig 22. rtc oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 18. recommended values for the rtc external 32 khz oscillator c x1 /c x2 components crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 /c x2 11 pf < 100 k ? 18 pf, 18 pf 13 pf < 100 k ? 22 pf, 22 pf 15 pf < 100 k ? 27 pf, 27 pf 002aaf495 lpc2xxx rtcx1 rtcx2 c x2 c x1 32 khz xtal = c l c p r s l
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 59 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 14.5 standard i/o pi n configuration figure 23 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? analog input (for adc input channels) the default configuration for standard i/o pi ns is input with pull-up enabled. the weak mos devices provide a drive capability equiva lent to pull-up and pull-down resistors. fig 23. standard i/o pin configuration with analog input pin v dd esd v ss esd v dd weak pull-up weak pull-down output enable output pull-up enable pull-down enable data input analog input select analog input 002aaf496 pin configured as digital output driver pin configured as digital input pin configured as analog input
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 60 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 14.6 reset pin configuration fig 24. reset pin configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 61 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 15. package outline fig 25. package outline sot407-1 (lqfp100) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1)(1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 62 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers fig 26. package outline sot926-1 (TFBGA100) references outline version european projection issue date iec jedec jeita sot926-1 - - - - - - - - - sot926-1 05-12-09 05-12-22 unit a max mm 1.2 0.4 0.3 0.8 0.65 0.5 0.4 9.1 8.9 9.1 8.9 a 1 dimensions (mm are the original dimensions) TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm a 2 b d e e 2 7.2 e 0.8 e 1 7.2 v 0.15 w 0.05 y 0.08 y 1 0.1 0 2.5 5 mm scale b e 2 e 1 e e 1/2 e 1/2 e ac b ? v m c ? w m ball a1 index area a b c d e f h k g j 246810 13579 ball a1 index area b a e d c y c y 1 x detail x a a 1 a 2
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 63 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 16. abbreviations table 19. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection can controller area network dac digital-to-analog converter dcc debug communication channel dma direct memory access dsp digital signal processing eop end of packet etm embedded trace macrocell gpio general purpose input/output irda infrared data association jtag joint test action group mii media independent interface miim media independent interface management phy physical layer pll phase-locked loop pwm pulse width modulator rmii reduced media independent interface se0 single ended zero spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port ttl transistor-transistor logic uart universal asynchronous receiver/transmitter usb universal serial bus
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 64 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 17. revision history table 20. revision history document id release date data sheet status change notice supersedes lpc2364_65_66_67_68 v.7.1 20131016 product data sheet - lpc2364_65_66_67_68 v.7 modifications: ? table 4 ? pin description ? , table note 6 : changed glitch filter spec from 5 ns to 10 ns. ? table 9 ? dynamic characteristics ? : changed min clock cycle time from 42 to 40. lpc2364_65_66_67_68 v.7 20111020 product data sheet - lpc2364_65_66_67_68 v.6 modifications: ? table 13 ?dynamic characteristics of flash?: added characteristics for t er and t prog . ? table 4 ?pin description?: updated description for usb_up_led. ? table 4 ?pin description?: added table note 12 ?if the rtc is not used, these pins can be left floating.? for rtcx1 and rtcx2 pins. ? table 4 ?pin description?: added table note 8 ?this pin has a built-in pull-up resistor.? for dbgen, tms, tdi, trst , and rtck pins. ? table 4 ?pin description?: added table note 7 ?this pin has no built-in pull-up and no built-in pull-down resistor.? for tck and tdo pins. ? table 5 ?limiting values?: added ?non-operating? to conditions column of t stg . ? table 5 ?limiting values?: updated ta ble note 5 ?the maximum non-operating storage temperature is differ ent than the temperature for required shelf life which should be determined based on required shelf lifetime. please refer to the jedec spec (j-std-033b.1) for further details.?. ? table 5 ?limiting values?: updated storage temperature min/max to ? 65/+150. ? added table 7 ?thermal resistance value (c/w): 15 %?. ? added table 10 ?dynamic characteristic: internal oscillators?. ? added table 11 ?dynamic characteristic: i/o pins[1]?. ? table 8 ?static characteristics?: changed v hys typ value from 0.5v dd(3v3) to 0.05v dd(3v3) . ? table 13 ?dynamic characteristics of flash?: updated table. ? added section 9 ?thermal characteristics?. ? added section 10.3 ?electri cal pin characteristics?. ? added section 14.2 ?crystal oscillator xtal input and component selection?. ? added section 14.3 ?rtc 32 khz oscillator component selection?. ? added section 14.4 ?xtal and rtcx printe d circuit board (pcb) layout guidelines?. ? added section 14.5 ?standard i/o pin configuration?. ? added section 14.6 ?reset pin configuration?.
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 65 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers lpc2364_65_66_67_68 v.6 20100201 product data sheet - lpc2364_65_66_67_68 v.5 modifications: ? table 5 ?limiting values?: changed v esd min/max to ? 2500/+2500. ? table 6: updated min, typical and max values for oscillator pins. ? table 6: updated conditions and typical values for i dd(dcdc)pd(3v3) , i batact ; i dd(dcdc)dpd(3v3) and i bat added. ? table 9 ?dynamic characteristics of flas h?: changed flash endurance spec from 100000 to 10000 minimum cycles. ? added table 11 ?dac electrical characteristics?. ? section 7.2 ?on-chip flash programming memory?: removed te xt regarding flash endurance minimum specs. ? added section 7.24.4.4 ?deep power-down mode?. ? section 7.25.2 ?brownout detection?: changed v dd(3v3) to v dd(dcdc)(3v3) . ? added section 9.2 ?deep power-down mode?. ? added section 13.2 ?xtal1 input?. ? added section 13.3 ?xtal and rtc printed- circuit board (pcb) layout guidelines?. ? added table note for xtal1 and xtal2 pins in table 3. lpc2364_65_66_67_68 v.5 20090409 product data sheet - lpc2364_65_66_67_68 v.4 modifications: ? added part lpc2364hbd100. ? section 7.2: added sentence clarifying sram speeds for lpc2364hbd. ? table 5: updated v esd min/max. ? table 6: updated z drv table note [14]. ? ta b l e 6 : v hys , moved 0.4 from typ to min column. ? ta b l e 6 : i pu , added specs for >85 ?c. ? table 6: removed r pu . ? table 7: cclk and irc, added specs for >85 ?c. ? added table 9. ? updated figure 14. ? updated figure 11. lpc2364_65_66_67_68 v.4 20080417 product data sheet - lpc2364_66_68 v.3 lpc2364_66_68 v.3 20071220 product data sheet - lpc2364_66_68 v.2 lpc2364_66_68 v.2 20071001 preliminary data sheet - lpc2364_66_68 v.1 lpc2364_66_68 v.1 20070103 preliminary data sheet - - table 20. revision history ?continued document id release date data sheet status change notice supersedes
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 66 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? 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lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 67 of 69 nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc2364_65_66_67_68 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 7.1 ? 16 october 2013 68 of 69 continued >> nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 functional description . . . . . . . . . . . . . . . . . . 18 7.1 architectural overview . . . . . . . . . . . . . . . . . . 18 7.2 on-chip flash programming memory . . . . . . . 19 7.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 20 7.5.1 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 21 7.6 pin connect block . . . . . . . . . . . . . . . . . . . . . . 21 7.7 general purpose dma controller . . . . . . . . . . 21 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.8 fast general purpose parallel i/o . . . . . . . . . . 22 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.9 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.10 usb interface (lpc2364/66/68 only) . . . . . . . 24 7.10.1 usb device controller . . . . . . . . . . . . . . . . . . . 24 7.10.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.11 can controller and acceptance filters (lpc2364/66/68 only). . . . . . . . . . . . . . . . . . . 25 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.12 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.13 10-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.14 uarts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.15 spi serial i/o controller. . . . . . . . . . . . . . . . . . 26 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.16 ssp serial i/o controller . . . . . . . . . . . . . . . . . 27 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17 sd/mmc card interface (lpc2367/68 only) . . 27 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18 i 2 c-bus serial i/o controllers. . . . . . . . . . . . . . 27 7.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.19 i 2 s-bus serial i/o cont rollers. . . . . . . . . . . . . . 28 7.19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.20 general purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 29 7.20.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.21 pulse width modulator . . . . . . . . . . . . . . . . . . 29 7.21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.22 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 30 7.22.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.23 rtc and battery ram . . . . . . . . . . . . . . . . . . 31 7.23.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.24 clocking and power control . . . . . . . . . . . . . . 31 7.24.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 31 7.24.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 32 7.24.1.2 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 32 7.24.1.3 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 32 7.24.2 pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.24.3 wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 32 7.24.4 power control . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.24.4.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.24.4.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.24.4.3 power-down mode . . . . . . . . . . . . . . . . . . . . . 34 7.24.4.4 deep power-down mode . . . . . . . . . . . . . . . . 34 7.24.4.5 power domains . . . . . . . . . . . . . . . . . . . . . . . 34 7.25 system control . . . . . . . . . . . . . . . . . . . . . . . . 35 7.25.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.25.2 brownout detection . . . . . . . . . . . . . . . . . . . . 35 7.25.3 code security (code read protection - crp) . . . . . . . . . . . 36 7.25.4 ahb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.25.5 external interr upt inputs . . . . . . . . . . . . . . . . . 36 7.25.6 memory mapping control . . . . . . . . . . . . . . . . 37 7.26 emulation and debugging . . . . . . . . . . . . . . . 37 7.26.1 embeddedice . . . . . . . . . . . . . . . . . . . . . . . . 37 7.26.2 embedded trace. . . . . . . . . . . . . . . . . . . . . . . 37 7.26.3 realmonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 39 9 thermal characteristics . . . . . . . . . . . . . . . . . 40 10 static characteristics . . . . . . . . . . . . . . . . . . . 41 10.1 power-down mode . . . . . . . . . . . . . . . . . . . . . 44 10.2 deep power-down mode . . . . . . . . . . . . . . . . 45 10.3 electrical pin characteristics. . . . . . . . . . . . . . 47 11 dynamic characteristics. . . . . . . . . . . . . . . . . 48 11.1 internal oscillators . . . . . . . . . . . . . . . . . . . . . 49 11.2 i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.3 usb interface. . . . . . . . . . . . . . . . . . . . . . . . . 49 11.4 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 50 11.5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 adc electrical characteristics . . . . . . . . . . . . 52 13 dac electrical characteristics . . . . . . . . . . . . 55 14 application information . . . . . . . . . . . . . . . . . 55
nxp semiconductors lpc2364/65/66/67/68 single-chip 16-bit/32-bit microcontrollers ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 16 october 2013 document identifier: lpc2364_65_66_67_68 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 14.1 suggested usb interface solutions (lpc2364/66/68 only). . . . . . . . . . . . . . . . . . . 55 14.2 crystal oscillator xtal input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.3 rtc 32 khz oscillator component selection . . 58 14.4 xtal and rtcx printed circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . 58 14.5 standard i/o pin configuration . . . . . . . . . . . . 59 14.6 reset pin configuration . . . . . . . . . . . . . . . . . . 60 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 61 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 64 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 66 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 66 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 67 19 contact information. . . . . . . . . . . . . . . . . . . . . 67 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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